High speed multiplier circuit



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Oct. 11, 1966 Filed 0st. 29, 1963 M. K. HAYNES HIGH SPEED MULTIPLIER CIRCUIT Oct. 11, 1966 19 Sheets-Sheet 17 Filed Oct. 29, 1963 T C U D 0 R DI 'L T R A P D N 0 AIV E 5 1 1 O 1 1 110 O 1 A a I 0 U Du 0 R P L Mi T" M P I 5 R fr 114 4 1 1 1 0000 O CONSOLIDATION SECOND O01 PRODUCT c E m D C D M A m 4 b d d 80d 80a 80b 80C FIG.15

Oct. 11, 1966 M. K. HAYNES 3,278,732

HIGH SPEED MULTIPLIER CIRCUIT FiledOct. 29, 1963 19 Sheets-Sheet 18 1 1 I 1 o 1 1 1 O O O O 1 1 1 1 0 1100071 FIRST PARTIAL PRODUCT 1'1 Z 'PARTIAL PRODUCT 0000 3 m.

101 1 SECOND PARTIAL PRODUCT OOOO THIRD PARTIAL PRODUCT I 11 I 100 FINAL PRODUCT FIG. 16b

R=2 s=3 c=1 ADDERS 40a 4411 40b 44b 40c 44c 40d 44d 80b 80a 90b 90a 2 E E E E 1 s6 E s6 s6 2 so 6 so sc 6 1 E5 E E's' cs 6 2 Es E5 Es 65 SC 6 1 5E 56 E5 56 c 2 6 's'E 6 56 E5 1 1 5 3 6s @6 0 2 '5 E 6@ 0 I 56 6(5) 2 @E: 1 1 @5 I 2 I 1 0 P S 8 FIG.16c|

United States Patent 3,278,732 HIGH SPEED MULTIPLIER CIRCUIT Munro K. Haynes, Chappaqua, N.Y., assiguor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Oct. 29, 1963, Ser. No. 319,783 20 Claims. (Cl. 235-164) This invention relates to multiplier circuits and more particularly to multiplier circuits using carry-save addition.

The times required to generate the sum and the carry in the adders of a multiplier circuit are often different and either or both of these times may be different from the recycle time of the logical elements in the adder. In order to synchronize the operation of the multiplier, it is generally necessary to delay either the sum output, the carry output, or both so that they arrive at the input of the next adder to use them in synchronization with each other and when that adder, having completed its recycled time, is ready to receive them. For example, if the adder generates a carry in one unit of time, a sum in two units of time, and uses logical elements having a recycle time four units long, the carry would have to be delayed three units of time and the sum two units before being applied to the next adder to use them. It can be seen that, in the above example, productive functions are being performed during only two units of a four unit cycle. If the delays generally employed in a multiplier of this type could be eliminated and productive operations performed during the entire recycle time of the adder elements, the efliciency and speed of the multiplier could be substantially increased.

It is therefore a general object of this invention to provide efiicient, high-speed, carry-save multipliers.

A more specific object of this invention is to provide carry-save multipliers which have productive operations being performed during the entire recycle time of the adder elements.

Another object of this invention is to provide carry save multipliers which require neither the sum output nor the carry output from an adder to be delayed before being applied to the next adder to utilize them. This object is compromised in some embodiments of the invention where delays are required before applying sum outputs to consolidation adders for partial products, but, as will be seen, these delays do not slow the operation.

A further'object of this invention is to provide an algorithm for designing carry-save multipliers of the type indicated above which does not require the sum or the carry to be delayed provided the recycle time of the adder elements and the sum time are integral multiples of the carry time.

In accordance with these objects, this invention provides multipliers which multiply using carry-save addition. The multiplier uses an array of R adders per multiplicand bit, each of which adders generates a carry in one unit of time, a sum in S units of time, andhas a repetition rate of R. In the multipliers being considered, S or R may be equal to 1, but at least S or R is greater than 1. The multiplicand bit is applied under control of the multiplier bits to one input of the adders of that bit, the multiplicand being applied to only one adder during each unit of time. The carry output from each adder is applied to a second input of the next adder for the same bit. The adders are considered to be formed in a closed ring so that a carry output from the last adder is applied as one input for the first adder for the same bit. The sum output from each adder is applied to a third input of an adder S bit positions and S adder positions ad- 3,278,732 Patented Oct. 11, 1966 ice vanced from the adder in which the sum is generated. This results in S partial products being generated. Where S is greater than 1, additional adders are provided for consolidating the S partial products into a final product.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIGS. l10 are schematic block diagrams of various embodiments of the invention.

FIG. 11 is a diagram showing how FIGS. 11a11b are combined to form a schematic block diagram of another embodiment of the invention.

FIGS. lla-llb, when combined, form a schematic block diagram of another embodiment of the invention.

FIG. 12 is a diagram showing how FIGS. 12a-l2c are combined to form a schematic block diagram of still another embodiment of the invention.

FIGS. l2a*12c, when combined, form a schematic block' diagram of still another embodiment of the invention.

FIG. 13 is a chart illustrating the operation of the embodiment of the invention shown in FIG. 1.

FIG. 14a is a chart illustrating the operation of the embodiment of the invention shown in FIG. 5.

FIG. 14b is an example showing how multiplication is performed in the embodiment of the invention shown in FIG. 5.

FIG. 15 is a chart illustrating the operation of the embodiment of the invention shown in FIG. 7.

FIG. 16a is a chart illustrating the operation of the embodiment of the invention shown in FIG. 9.

FIG. 16b is an example showing how multiplication is performed in the embodiment of the invention shown in FIG. 9.

FIG. 17 is a schematic block diagram of a digit circulator suitable for use either as is or in modified form in the embodiments of the invention shown in FIGS. l-lO, lla-llb and 1241-120.

FIG. 18 is a schematic block diagram of an adder suitable for use in the embodiments of the invention shown in FIGS. 8-10 and 11a-11b.

FIG. 19 is a schematic block diagram of an adder suitable for use in the embodiments of the invention shown in FIGS. 4-7.

In describing the various embodiments of the invention shown in FIGS. l-lO, Ila-11b and l2a-12c, inputs and outputs are said to occur at various phases. For purposes of the present discussion, a phase may be con- .sidered to be an integral sub-multiple of the recycle time of the logical'element being employed. For example, if the logical elements being employed have a recycle time of 4, the circuit Will have four phases. In the figures, the numbers appearing in each block or part of a block indicate the phase at which that block or part of block generates an output. An input to that block occurs during the preceding phase. The blocks are lined up so that all adders or part of adders in a given horizontal row generate an output at the same phase.

Also, in discussing the figures, the letters, S, C, and R are employed. The significance of these letters are as follows:

S=the number of phases required by the adders to genrate a sum output (i.e., the time delay of the sum output).

C=the number of phases required by the adders to generate a carry output (i.e., the time delay of the carry output).

R=the number of phases required by the logical ele- 

3. A CIRCUIT FOR MULTIPLYING A N-BIT MULTIPLICAND BY AN M-BIT MULTIPLIER COMPRISING: AN ARRAY OF ADDERS WITH R ADDERS PER MULTIPLICAND BIT, EACH OF SAID ADDERS HAVING A CARRY-DELAY TIME OF C, A SUM-DELAY TIME OF S AND A RECYCLE TIME FOR ITS LOGICAL ELEMENTS OF R, WHERE S AND R ARE INTEGRAL MULTIPLES OF C AND AT LEAST ONE OF THEM IS GREATER THAN C; MEANS FOR APPLYING EACH BIT OF THE MULTIPLICAND TO THE ADDERS FOR THAT BIT UNDER CONTROL OF THE BITS OF THE MULTIPLIER; MEANS FOR APPLYING THE CARRY OUTPUT FROM EACH ADDER TO THE NEXT ADDER TO BE UTILIZED FOR THE SAME MULTIPLICAND BIT; MEANS FOR APPLYING THE SUM OUTPUT FROM EACH ADDER TO THE ADDER S MULTIPLICAND BIT POSITIONS AND S ADDER POSITIONS ADVANCED FROM THE ADDER GENERATING THE SUM OUTPUT; WHEREBY S PARTIAL PRODUCTS ARE FORMED; AND AN ARRAY OF R(S-1) CONSOLIDATION ADDERS FOR CONSOLIDATING SAID S PARTIAL PRODUCTS INTO THE FINAL PRODUCT. 